Referring to FIG. 1, a conventional flash memory structure 1 includes a substrate 11, a source 12, a drain 13, a tunnel isolation layer 14, a charge-trapping layer 15, a blocking isolation layer 16 and a gate 17. The source 12 is formed on the substrate 11. The drain 13 is formed on the substrate 11 and spaced apart from the source 12. The tunnel isolation layer 14 is formed on the substrate 11. The charge-trapping layer 15 is formed on the tunnel isolation layer 14. The blocking isolation layer 16 is formed on the charge-trapping layer 15. The gate 17 is formed on the blocking isolation layer 16.
Referring to FIG. 2, it is a read-write data map of a gate voltage VG (unit: V) vs. a drain current parameter ID (unit: A/um) when the conventional flash memory structure 1 performs reading and writing during different gate voltage sweeps. As shown in FIG. 2, the conventional flash memory structure 1 has a large writing/erase voltage (greater than 15 V) and the minimum value of its Subthreshold Swing (S.S.) is 60 mV/dec. As a general high dielectric permittivity material, e.g., HfO2, is used as the blocking isolation layer 16, the conventional flash memory structure 1 has a large leakage current and a poor S.S. and requires a large voltage to open a memory window.
FIG. 3 is a measuring data map of time (unit: ms) vs. a gate operating voltage (unit: V) and a drain current (unit: μA) of the conventional flash memory structure 1. As shown in FIG. 3, the speed of the reading-writing operation of the conventional flash memory structure 1 is slow, which is about 100 μs to 1 ms, because a general high dielectric permittivity material, e.g., HfO2, is used as the blocking isolation layer 16 (FIG. 1).
The conventional flash memory structure 1 has a slow operating speed (about 100 μs to 1 ms), a large writing/erase voltage (e.g., greater than 15 V) and poor operation durability (about 105 cycles). However, the basic transistor physical phenomenon of the conventional flash memory structure 1 makes the minimum value of the S.S. be 60 mV/dec, and the operating voltage and switch power consumption cannot further be reduced. In response to a future high-density memory technical demand, development of the flash memory with a fast operating speed and low power consumption is necessary.